Integrated circuit fabrication processes and techniques commonly would produce unacceptable nonplanar surface topography on the devices produced if planarizing steps were not taken at various stages of the processing. Of course, each additional layer of processing which is itself nonplanar can add to the irregularities of the finally produced device surface. Such irregularities are commonly called steps where an applied film is required to cover two or more levels of a surface. Such steps commonly cause problems in the devices produced because the film is typically thinned in the area of the step. Depending on the material of the film, the conductivity or insulating properties of the film are degraded in the area of the step. During heat, current, or mechanical stress of these steps, the films have been known to break or become discontinuous at the step causing the device to fail. If the step is too large, if the material applied to the step is not sufficiently conformal, or if a combination of these factors occurs, the film may not be continuous over the step or voids may form between two film layers. Also, a problem with fabrication of devices having nonplanar surface features is the fact that the depth of field of known photolithographic steppers becomes very small as feature size becomes less than 1 micron. Therefore, precise focus on such nonplanar surfaces becomes impossible. Devices produced by multilevel metallization techniques wherein two or more layers of patterned metal film crisscross a device to provide lead lines, such as bit lines and word lines of semiconductor memory devices, are typical of the type of device in which planarization steps are desirable during device fabrication.
Several methods in the prior art have been devised to planarize a nonplanar surface of semiconductor devices. For example, a liquid or easily planarized material may be applied to such a surface. A photoresist material is commonly used. The photoresist may be spun on the surface. The photoresist or other material must have the additional property that it has the same or similar etch selectivity as the underlying material of the nonplanar surface with respect to a specific etchant. Then the photoresist planar-surfaced layer is removed completely by this etchant and the nonplanar topography of the underlying layer is also etched to leave a planar surface on the underlying layer. It is commonly necessary then to add to the underlying layer that has been partially removed to insure the required electrical properties of this layer are maintained. This planarization method is detailed in U.S. Pat. No. 4,795,722, issued 1-3-89, to M. Torreno, et al (Ser. No. 010,937), and incorporated herein by reference. This method is not entirely satisfactory in all processes because it adds extra processing steps, depends on the etching properties of the materials, requires an easily planarized material that is sacrificed during the process, and requires careful timing of the etch step.
Other planarization methods are known in the art. For example, furnace or laser reflow is used to reduce the step coverage problems. These methods do not generally produce a truly planar surface, however, and the heat required is sometimes damaging to the device. Also, the dielectric layer required on the device may be spun on to produce a planar surface. However, most dielectrics commonly used cannot be easily spun on to a device. The layer may also be deposited by bias sputtering. However, this method is not always available for all devices and processes and is not capable of producing a good dielectric layer in all cases.
It is also known to polish a blank semiconductor substrate by strictly mechanical means and combined chemical-mechanical means prior to any other processing to remove surface defects and impurities and to produce the very high tolerance flatness and smoothness necessary for critical photolithographic steps and other steps in integrated circuit processing. Several methods and apparatuses are known in the art to accomplish this polishing of single crystal silicon wafers or other semiconductor wafers. Basically mechanical polishing is accomplished by frictional application of a slightly abrasive surface to the surface of the wafer. For example, a circular flat disc can be rotated steadily while a wafer, or more than one wafer, is held by steady and precise pressure stationary against the disc. The disc may be abrasive, in which case it is common to apply deionized water at the interface to carry away particles and reduce heat build up. Also, an abrasive slurry may be introduced to the interface. The slurry can contain mechanically abrasive particles, chemically abrasive compounds, or a mixture of both. Another example of such known polishing processes is to hold a wafer in a lathe-like device and rotate the wafer while applying a cutting device, such as a diamond point stylus or an abrasive surface, steadily across the wafer as it turns. In this example, a liquid is also commonly applied in a similar manner as described in the previous example.
Such polishing techniques and apparatuses have been considered to be "dirty" in that they could introduce foreign elements to the wafer such as from the polishing means. As used for polishing, these devices and processes typically were not closely controlled since it was not at all critical at that processing stage how much of the wafer as removed.